The invention relates to a circuit arrangement for the processing of binary signals.
The article xe2x80x9cA VLSI System for Real-Time Linear Operations and Transformsxe2x80x9d, published in IEEE Transactions on Signal Processing, Vol. 39, book 8, August 1991, pp. 1914 to 1917, describes a VLSI system for the calculation of products of vector matrices which includes a double clock diagram with which circuit elements can be controlled so as to perform identical calculation operations in the multiplex mode. Because of such multiple use of the circuit elements, the highest permissible operating frequency is made available in the circuit for an external data bandwidth, offering an improved ratio of the signal processing capacity to the circuit requirements in respect of crystal surface area in an integrated circuit arrangement. A system is described in which an internal clock frequency is four times higher than the clock frequency of the externally supplied data. The internal clock frequency in one example amounts to 40 MHz whereas the frequency on an output data bus amounts to only 10 MHz.
The conference proceedings xe2x80x9cVLSI Signal Processing, IIIxe2x80x9d, published in IEEE Press, New York, USA, 1988, pp. 50 to 60, xe2x80x9cSpeech Codec Architecture for Pan-European Digital Mobile Radio Using Bit-Serial Signal Processingxe2x80x9d discloses the construction of an integrated circuit for the encoding of speech signals which is intended notably for digital mobile radio. The algorithm used for such encoding is implemented in a bit-serial circuit structure without programmable parts. Critical circuit elements between different function blocks of the system operate in time multiplex in said circuit structure. The aim is to achieve a significant reduction of the surface area for the circuit as well as a reduction of the power consumption. The time multiplex used therein operates in such a manner that circuit elements which are only temporarily required are also used by other circuit elements during their idle time which usually covers several continuous clock periods.
It is an object of the invention to construct a circuit arrangement of the kind set forth in such a manner that, on the basis of an arrangement in which binary signals are internally processed with the same repetition frequency as that at which their output signals occur, a simple, fast and clear circuit concept is possible for operation at an internal repetition frequency which is higher than the repetition frequency of the output signal and at least substantially independent of the signal processing to be carried out.
The object according to the invention is achieved by means of a circuit arrangement for the processing of binary signals which includes:
at least one logic arrangement for outputting each time at least one binary output signal, and
for each logic arrangement at least one storage arrangement for storing the binary output signal, or the binary output signals, at instants which are defined by a clock signal which exhibits state transitions which occur in a cyclical sequence,
at least one of the storage arrangements including a number of storage cells, each of which includes a respective output and stores, at the instant of an associated state transition within each of the cycles of the clock signal, the instantaneous value of each time one of the binary output signals and outputs it via its output, the outputs of the storage cells of each time one of the storage arrangements being connected to a common output of the relevant storage arrangements a switching stage whereby the output of each storage cell is connected, in the time interval which commences with the associated state transition of the clock signal and terminates with the next state transition of the clock signal in the cyclical sequence, to the common output of the relevant storage arrangement.
The circuit arrangement according to the invention is segmented in such a manner that the logic arrangement and the storage arrangement or arrangements are arranged so as to be functionally separated and preferably also spatially separated from one another. For operation of this circuit arrangement, during which the internal signal processing takes place at the same repetition frequency, notably within the logic arrangement (arrangements), as that of the output of the output signals, the storage arrangement or arrangements can be constructed in a conventional manner, the internal signal processing and output signals preferably being controlled at the same clock frequency.
However, if the described circuit arrangement is provided with a storage arrangement according to the invention instead of with a conventional storage arrangement(s), it is possible, without making any additional modifications, to operate such that a number of signal processing steps which corresponds to the number of state transitions of the clock signal within each cycle can be executed during each of the cycles of the clock signal. The values of the output signal or output signals of the logic arrangement (arrangements) resulting from these individual processing steps within a cycle are stored in each time a respective one of the storage cells of the storage arrangement (arrangements). This enables multiple use of the logic arrangement within a cycle of the clock signal. A saving in respect of circuit elements is thus achieved, because the logic arrangement (arrangements) need no longer be provided in parallel in a number which corresponds to the number of state transitions within a cycle of the clock signal.
A particularly significant saving in respect of circuit elements is achieved for circuit arrangements in which the logic arrangement (arrangements) is (are) very large in comparison with the storage arrangement or storage arrangements. Dual use of the logic arrangement (arrangements) can then save a high percentage of circuit elements, preferably crystal surface area in the case of integrated circuits, because the storage arrangement (arrangements) constructed according to the invention require only few circuit means. When a circuit arrangement of this kind has a plurality of logic arrangements and a plurality of storage arrangements, the principle of the invention is applied to as many of these storage arrangements as possible so that the saving is maximized.
A particularly simple embodiment of the circuit arrangement according to the invention is obtained when at least one of the storage arrangements includes two storage cells which are constructed as D-flipflops and whose clock inputs can be supplied with a clock signal in the form of an at least approximately square-wave signal, a first one of the D-flipflops of the storage arrangement (arrangements) being driven by the ascending edge for the purpose of storage whereas the second one of the D-flipflops is driven by the descending edge, the switching stage being controlled in conformity with the levels of the clock signal between the state transitions.
A circuit arrangement having such a construction enables the repetition frequency of the internal signal processing to be increased to double the clock frequency, it merely being necessary to replace conventional storage arrangements by those according to the invention. In each cycle of the clock signal two signal values can be processed independently of one another. It is notably possible to process two completely independent binary signals in a logic arrangement and to store these signals in the two storage cells of the storage arrangement (arrangements) without mutual influencing.
Preferably, the instantaneous values of the binary output signals at the instants of corresponding state transitions in successive cycles of the clock signals are associated with a respective, separate data stream. This is because the invention particularly simply enables bit by bit processing of such separate data streams in a time-interleaved manner within each of the cycles of the clock signal, without mutual influencing, by the same logic arrangement (arrangements). For the bit by bit processing of two interleaved data streams, i.e. for the processing of two binary signals instantaneous value by instantaneous value, notably a first one of the data streams is processed in such a manner that its instantaneous values are stored during the ascending edges of the clock signal whereas the instantaneous values of the second signal are stored during the descending edges of the clock signal.
In the circuit arrangement according to the invention the processed data streams appear bit interleaved on the common output of the switching stage, or on the common outputs of the switching stages, for further processing in the same way.
However, the binary signals on such a common output can be de-interleaved at any time by a demultiplexing operation which can be simply controlled by the clock signal. This enables very simple combination of serial processing of the signals and their parallel output.
The invention can be very universally used for a variety of products for electronic data processing. In an example of an application for the drive of a xe2x80x9cController Area Networkxe2x80x9d (CAN), the repetition frequency of the serial data processing could be doubled while adding only 7.5% to the circuit means.